MLDesigner provides you with the ability to check the FSM design for semantic errors.
If an FSM design contains errors, a message occurs and all semantic errors are listed. This FSM design check is done automatically while saving a finite state machine model. The following semantic rules for states, default entrances, and histories are checked in association with the FSM design objects.
Hierarchical states can also be reached by transitions, that is, the source state is a state outside the hierarchical state and the target state is a descendant state of the hierarchical state. Hierarchical states can also be left by inherited transitions or by transitions, that is, the source state is a descendant state of the hierarchical state and the target state is a state outside of the hierarchical state. States must not have synchronous self transitions without a guard condition, since such transitions are 100% candidates for infinite loops. There are a lot of ways to create infinite loops in a finite state machine, but they can not all be detected by the FSM semantic check.