Tier 2 Domains

Synchronous Reactive

The Synchronous Reactive (SR) domain is a very experimental domain. SR is a statically-scheduled simulation domain in MLDesigner designed for concurrent, control-dominated systems. To allow precise control over timing, it adopts the synchronous model of time, which is logically equivalent to assuming that computation is instantaneous.

SR differs from other MLDesigner domains in several important ways. Like SDF, it is statically scheduled and deterministic, but it does not have buffered communication or multi-rate behavior. SR is better for control-dominated systems that need control over when things happen relative to each other - whereas SDF is better for data-dominated systems, especially those with multi-rate behavior.

The domain also resembles the DE domain. Its communication channels transmit events, but unlike DE, it is deterministic, statically scheduled, and allows zero-delay feedback loops. DE is better for modeling the behavior of systems (i.e., to better understand their behavior), whereas SR is better for specifying a system’s behavior (i.e., as a way to actually build it).

Boolean Data Flow

Like DDF, the BDF domain supports run-time flow of control. Unlike DDF, it attempts to construct a compile-time schedule. Thus it achieves the efficiency of SDF with the generality of DDF. It currently supports a somewhat more limited range of primitives than DDF, and does not support recursion, but the model of computation is, in principle, equally general. Its applications are the same as those of DDF.

The basic mechanism used in BDF is to construct an annotated schedule, by which is meant a static schedule where each firing in the schedule is annotated with the Boolean conditions under which it occurs. Thus, any sequence of firings can depend on a sequence of boolean values computed during the execution. Executing the annotated schedule involves much less overhead than executing a dynamic data flow schedule.

Multidimensional Synchronous Data Flow

The MDSDF domain is an extension of the SDF model to multidimensional streams and is based on the work of Edward A. Lee. It provides the ability to express a greater variety of data flow schedules in a graphically compact way. It also allows nested reset-table loops and delays. Additionally, MDSDF has the potential for revealing data parallelism in algorithms. The current implementation only allows two dimensional streams, although we hope that many of the ideas used in the development of the domain can be generalized to higher dimensions.

Code Generation

The CG domain is a base domain from which all other code generation domains are derived. This domain supports a general data flow model equivalent to SDF and BDF. The primitives in this domain do little more than generate comments when fired, but they can serve to demonstrate and test the features of scheduling algorithms. In this domain, you can build test systems, view the generated code (comments) for multiple processors, and display a Gantt chart for parallel schedules. In derived domains, real code is generated, compiled, downloaded and executed, all under control of the selected target. One weakness of all code generation domains is that they only scalar data types (complex, floating-point, integer, and fixed-point) are supported on the input and output ports.

Code Generation C

The CGC domain uses Boolean-controlled data flow semantics, and has ANSI C as its target language. We have made every effort to name primitives and their parameters consistently so that it is easy to move from one domain to another. With a little effort, one could create CGC versions of all SDF primitives. If this were accomplished, then re-targeting from one domain to another would be a simple matter of changing domains and targets and running the system again.

The generated ANSI C code is statically scheduled, and the memory used to buffer data between primitives is statically allocated. Moreover, for many of the primitives, the code that is generated depends on the values of the parameters. One way to think of this is that the parameters of the primitive are evaluated at code generation time, so no run-time overhead is incurred from the added flexibility of parameterizing the primitive.

There are several targets to choose from in the CGC domain. The bdf-CGC target supports the boolean-controlled data flow model of computation. It must be used whenever primitives with BDF semantics are present in a program graph. The default-CGC target supports the SDF model of computation, so it can be used when the program graph contains only primitives with SDF semantics. The TclTk-Target target also supports SDF, and must be used whenever Tcl/Tk primitives are present in the program graph. The unixMulti-C target supports SDF and partitions the program graph for execution on multiple workstations on a network.

Code Generation for Motorola DSP56000

The CGC56 domain synthesizes assembly code for the Motorola DSP56000 family. This domain has been used to generate real-time implementations of various modem standards, touch tone generators, and touch tone decoders.

Code Generation VHDL

The domains VHDL and VHDLB are designed for generating code in VHDL (VHSIC Hardware Description Language). The VHDL domain supports functional models using the SDF model of computation, while VHDLB supports behavioral models using the native VHDL discrete event model of computation. Since the VHDL domain is based on the SDF model, it is independent of any notion of time. The VHDLB domain supports time delays and time-dependent behavior of blocks. The VHDL domain is intended for modeling systems at the functional block level, as in DSP functions for filtering and transforms, or in digital logic functions, independent of implementation issues. The VHDLB domain is intended for modeling the behavior of components and their interactions in system designs at all levels of abstraction.

Within the VHDL domain there are a number of different targets to choose from. The default target, default-VHDL, generates sequential VHDL code in a single process within a single entity, following the execution order from the SDF scheduler. This code is suitable for efficient simulation, since it does not generate events on signals. The SimVSS-VHDL target is derived from default-VHDL and it provides facilities for simulation using the SYNOPSYS VSS VHDL simulator. Communication actors and facilities in the SimVSS-VHDL target support code synthesis and co-simulation of heterogeneous CG systems under the CompileCGSubsystems target developed by Jos`e Luis Pino. There is also a SimMT-VHDL target for use with the Model Technology VHDL simulator. The struct-VHDL target generates VHDL code where individual actor firings are encapsulated in separate entities connected by VHDL signals. This target generates code which is intended for circuit synthesis. The Synth-VHDL target, derived from struct-VHDL, provides facilities for synthesizing circuit representations from the structural code using the SYNOPSYS Design Analyzer tool set. Because the VHDL domain uses SDF semantics, it supports re-targeting from other domains with SDF semantics (SDF, CGC, etc.) provided that the primitives in the original graph are available in the VHDL domain. As this experimental domain evolves, more options for VHDL code generation from data flow graphs will be provided. These options will include varying degrees of user control and automation depending on the target and the optimization goals of the code generation, particularly in VHDL circuit synthesis.

Unlike the VHDL domain, the VHDLB domain is much simpler in its operation. When a system in the VHDLB domain is run, the graph is traversed and a code file is generated.