Bibliography

B1

Edward A. Lee and David G. Messerschmidt. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing. IEEE Trans. Computers, 36(1):24–35, January 1987.

B2

Edward A. Lee and David G. Messerschmidt. Synchronous Data Flow. Proc. of the IEEE, 75(9):1235–1245, September 1987.

B3

Joseph T. Buck, Soonhoi Ha, Edward A. Lee, and David G. Messerschmidt. Multirate Signal Processing in Ptolemy. In Proc. of Int. Conf. on Acoustics, Speech, and Signal Processing, volume 2, pages 1245–1248, Toronto, Canada, April 1991.

B4

Joseph T. Buck and Edward A. Lee. The Token Flow Model. In L. Bic, G. Gao, and J. Gaudiot, editors, Advanced Topics in Dataflow Computing and Multithreading. IEEE Computer Society Press, 1993.

B5

Joseph T. Buck and Edward A. Lee. Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model. In Proc. of Int. Conf. on Acoustics, Speech, and Signal Processing, volume I, pages 429–432, Minneapolis, MN, April 1993.

B6

Joseph T. Buck. Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model. PhD thesis, University of California, Berkeley, CA, September 1993.

B7

Edward A. Lee. Consistency in Dataflow Graphs. IEEE Trans. Parallel and Distributed Systems, 2(2):223–235, April 1991.

B8

Jos Luis Pino, Soonhoi Ha, Edward A. Lee, and Joseph T. Buck. Software Synthesis for DSP Using Ptolemy. J. on VLSI Signal Processing, 9(1):7–21, January 1993.

B9

Praveen K. Murthy. Multiprocessor DSP Code Synthesis in Ptolemy. University of California, Berkeley, CA, 1993. Memorandum No. UCB/ERL M93/66.

B10

Anthony Wong. A Library of DSP Blocks and Applications for the Motorola DSP96000 Family. EECS Dept., University of California, Berkeley, CA, May 1992. M.S. Report, Plan II.

B11

Asawareeand Kalavade and Edward A. Lee. A Hardware/Software Codesign Methodology for DSP Applications. IEEE Design and Test of Computers, 10(3):16–28, September 1993.

B12

Shuvra S. Bhattacharyya and Edward A. Lee. Looped Schedules for Dataflow Descriptions of Multirate Signal Processing Algorithms. Formal Methods in System Design, 5(3), December 1994. Updated from Technical Report UCB/ERL M93/37, EECS Dept., University of California, Berkeley, CA, May 21, 1993.

B13

Shuvra S. Bhattacharyya, Joseph T. Buck, Soonhoi Ha, and Edward A. Lee. A Scheduling Framework for Minimizing Memory Requirements of Multirate DSP Systems Represented as Dataflow Graphs. In L. Eggermont, P. Dewilde, E. Deprettre, and J. van Meerbergen, editors, VLSI Signal Processing VI. IEEE Special Publications, New York, NY, 1993.

B14

Shuvra S. Bhattacharyya, Joseph T. Buck, Soonhoi Ha, and Edward A. Lee. Generating Compact Code from Dataflow Specifications of Multirate Signal Processing Algorithms. IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 42(3):138–150, March 1995. Updated from Technical Report UCB/ERL M93/36, EECS Dept., University of California, Berkeley, CA, May 21, 1993.

B15

Shuvra S. Bhattacharyya and Edward A. Lee. Scheduling Synchronous Dataflow Graphs for Efficient Looping. J of VLSI Signal Processing, December 1993.

B16

Shuvra S. Bhattacharyya and Edward A. Lee. Memory Management for Dataflow Programming of Multirate Signal Processing Algorithms. IEEE Trans. on Signal Processing, 42(5), May 1994. Updated from Technical Report UCB/ERL M92/128, EECS Dept., University of California, Berkeley, CA, November 28, 1992.

B17

Soonhoi Ha and Edward A. Lee. Compile-Time Scheduling and Assignment of Dataflow Program Graphs with Data-Dependent Iteration. IEEE Trans. Computers, 40(11):1225–1238, November 1991.

B18

Soonhoi Ha. Compile-Time Scheduling of Dataflow Program Graphs with Dynamic Constructs. PhD thesis, University of California, Berkeley, CA, April 1992.

B19

Gilbert C. Sih and Edward A. Lee. A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. IEEE Trans. Parallel and Distributed Systems, 4(2), February 1993.

B20

Gilbert C. Sih and Edward A. Lee. Declustering: A New Multiprocessor Scheduling Technique. IEEE Trans. Parallel and Distributed Systems, 4(6):625–637, June 1993.

B21

Edward A. Lee. Architectures for Statically Scheduled Dataflow. In M. A. Bayoumi, editor, Parallel Algorithms and Architectures for DSP Applications, pages 159–190. Kluwer Academic Publishers, Boston, MA, 1991.

B22

S. Sriram and Edward A. Lee. Design and Implementation of an Ordered Memory Access Architecture. In Proc. of Int. Conf. on Acoustics, Speech, and Signal Processing, volume I, pages 345–348, Minneapolis, MN, April 1993.

B23

S. A. Edwards. The Specification and Execution of Heterogeneous Synchronous Reactive Systems. PhD thesis, University of California, Berkeley, CA, 1992.

B24

J.B. Dennis. First version of data flow procedure languange. Technical Report MAC TM61, MIT Laboratory for Computer Science, May 1975.